SoC Physical Design Engineer

Extending our international team, we are looking for a SoC Physical Design Engineer (Entry-Level).

Racyics® is Europe's leading design service provider for mixed-signal system-on-chip design and turnkey services in advanced nodes.

We deliver professional analog, digital and mixed-signal design services tailored to the customers' needs with focus on realization of complex System-on-Chips in leading edge technology nodes. Our team of more than 100 employees covers the complete chip design process up to system architecture development. Racyics is working for major German and international semi-custom companies both as a service provider and in collaborative partnerships.

• Contribute to physical design, implementation and verification of complex digital and mixed signal SoCs
• Implementation according to customer requirements using state-of-the-art EDA tools and flows
• Support individual steps in RTL2GDS flow like Synthesis, P&R, Physical Verification, EMIR, Equivalence Check or Static Timing Analysis
• Address challenges in designing SoCs in leading edge Technologies
• Contribute to methodology developments with proposals and implementation of flow and methodology enhancements

• ## Requirements:
• Bachelor's/Master's Degree in Electrical Engineering or Information Technology or similar
• Experience in Physical Implementation in leading edge CMOS technologies
• Basic knowledge of state-of-the-art synthesis, P&R and verification tools from Cadence, Synopsys, Ansys and Mentor
• Self-driven and hands-on way of working
• Strong analytical and solution-oriented thinking
• Good written and oral communication skills in English
• Team-player
• ## A plus would be:
• Experience with Digital-IC-EDA tools from Cadence, Synopsys and Siemens
• Experience in RTL2GDS in leading edge CMOS and/or FDSOI technologies
• Knowledge in timing modelling and timing analysis for digital designs
• Good written and oral communication skills in German